The present invention relates to a semiconductor device having a dual-port memory circuit and, more particularly, to a configuration of a replica circuit in the dual-port memory circuit. For example, the invention relates to a technique effectively applied to a system-on-chip (SOC) microcomputer.
In a memory circuit, an internal timing is generated by using a replica circuit including replica cells having the same transistor placement as that of memory cells. For example, a sense amplifying timing for signals read from complementary bit lines can be generated in accordance with characteristics of a memory cell. Without making an operation margin which is fixedly set in advance relatively large, process variations and the like can be handled. Patent document 1 describes an example of using replica memory cells in a single-port SRAM. In the example, a block of replica memory cells is added to an array in which normal memory cells to be selected according to an access address are disposed.    Patent document 1: Japanese Unexamined Patent Publication No. 2007-128603